Field of the Invention
This invention relates to the field of data processing systems. More particularly, this invention relates to the control of the memory interface within a data processing system.
Description of the Prior Art
It is known to provide data processing systems formed of a plurality of memory transaction masters communicating via interconnect circuitry. This is a popular form of design for system-on-chip integrated circuits. The interconnect circuitry can have a variety of forms and may, for example, be built in accordance with the AXI protocol developed by ARM Limited of Cambridge, England.
In order to increase processing performance it is known to provide transaction master circuitry, such as processor cores, with local cache memories which are coupled to a main memory via the interconnect circuitry. While this approach increases performance by permitting the processors quicker access to data stored within their local cache memory, it introduces the difficulty that coherency must be managed and controlled between the cache memories and the main memory. For example, two different cache memories may store a local copy of data held within the main memory. If the copy of the data stored within one of the cache memories is updated, then an access to the data within another of the cache memories, or within the main memory, could produce an out-of-date result. In order to deal with these difficulties, it is known to provide coherency control mechanisms within such systems. Typically these coherency control mechanisms issue snoop requests when a memory access is made. These snoop requests are issued to the other places within the memory system where a copy of that same data may be held. The snoop requests determine whether or not a more up-to-date version of that data exists elsewhere, as well as controlling other aspects of the access to such shared data, such as the status of the data, for example, shared or unique data and clean or dirty data.
The snoop control mechanisms are effective in controlling coherency, but suffer from the disadvantage of introducing additional overhead in the design, both in terms of circuit area, cost and energy consumption. Furthermore, it is also desirable to be able to connect transaction masters to coherent memory systems in circumstances where those transaction masters were not originally intended to operate within an environment where coherency control was necessary. Such legacy transaction masters typically will not include a local cache memory with coherency control mechanisms, such as the ability to respond and manage snoop requests. One possibility would be to add such a cache memory with a normal coherency capability to the transaction masters. However, this would represent a disadvantageous additional overhead, particularly when the transaction master does not have memory access requirements that otherwise justify the inclusion of such a cache memory permitting it to hold local copies of data values.
One way of addressing this problem is described in commonly assigned copending application No. U.S. Ser. No. 12/656,538 filed on 2 Feb. 2010 entitled Area and Power Efficient Data Coherency Maintenance.